Authors : Afaq Ahmad , Ali Jawad Al-Lawati and Ahmed Mohammed Al-Naamany
Abstract: Testing is an essential process to monitor the correct functioning of systems. In number of cases the testing cost amounts 40 – 50% of the total cost of the system itself. Coupled with this, is the problem of increase of density of integration of subsystems (nodes); causing the reduction of overall controllability of the system to such an extent, where testing becomes impossible even with the use of even with powerful automatic test pattern generator (ATPG) tools. Pseudo-random (PR) pattern testing is attractive for built-in self-test (BIST) because of the low overhead of the PR test pattern generator. But PR testing has the disadvantage that the fault coverages are mostly low because of the random pattern resistant faults (RPRF). Test point insertion (TPI) can be used to improve the testability of a circuit by removing the RPRFs. This study proposes the design and use of such a user-friendly simulated tool to compute and scan the complete controllabilities (CO) and fault cover (FC) information of any digital system networks at each of its nodes. Based on the knowledge of these information the imaginary points of TPI can be located and further, computations of CO and FC can be done in a recursive process to get the optimal location for the TPI.
Afaq Ahmad , Ali Jawad Al-Lawati and Ahmed Mohammed Al-Naamany , 2004. Identification of Test Point Insertion Location via Comprehensive Knowledge of Digital System`s Nodal Controllabilty Through a Simulated Tool . Asian Journal of Information Technology, 3: 142-147.