Abstract: In this study, micro core engines are designed for computation of predict and update outputs based on lifting scheme 9/7 Discrete Wavelet Transform (DWT) to reduce the time delay. The micro core engines are integrated into pipeline architecture for computation of 1D/2D and 3D-DWT. The 3D-DWT architecture is designed to process a 512x512 image with eight groups of frames sequentially with an improved throughput. The first stage computes 1D-DWT along the rows using four parallel processors. The memory interface with FIFO is implemented to reduce the latency between the first stage and the second stage that computes 2D-DWT along the column. The 3D-DWT is introduced to computes wavelet coefficients in the temporal direction and it is designed to operate at 512x4 clock cycles in sequence with 1D and 2D-DWT computations. The FIFO is implemented at the intermediate stages of the design tosynchronize the data movement in pipeline in all three stages. The memories attached to the input and output of every stage are designed to store the parallel processed data. The proposed architecture is suitable for high frequency and low power applications. Using the 9/7 filter for DWT computation reduces hardware complexity, memory accesses and achieves minimum error during reconstruction of images. The proposed architecture systematically combines hardware optimization techniques to develop a flexible DWT architecture that has high performance and is suitable for portable, high speed, low power applications. The 3D-DWT architecture has been implemented on Virtex-5 FPGA with utilizing of 51% of its slice registers with the frequency of operation is 373 MHz and the designed DWT-IDWT can be used as IP Core.