Authors : N.J.R. Muniraj and R.S.D. Wahidhabanu
Abstract: This study proposes the implementation of Filtered X-LMS algorithm into VLSI using Verilog HDL for active noise control applications. This ASIC chip was designed, simulated and synthesized using Xilinx FPGA Virtex 2P (2vp40ff1148-6) and the workability of the algorithm was tested for noise cancellation and verified using MATLAB. The operating frequency was about 24 MHZ.
N.J.R. Muniraj and R.S.D. Wahidhabanu , 2007. A New Technique to Implement Filtered X-LMS Algorithm for Active Noise Control Applications Using Reconfigurable Logic . Journal of Engineering and Applied Sciences, 2: 864-869.