Abstract: Serpent cipher had been designed as an alternative for the previous encryption standard algorithm, the data encryption standard. It had been chosen within the shortlist by the National Institute of Standard and Technology which eventually selected Rijndael cipher as an Advanced Encryption Standard. There is no doubt on the security of Serpent, however because of the high number of rounds it has slower implementation speed compared to the chosen algorithm. All over, it is important to design an efficient hardware implementation for a well-known algorithm as an option in case the current standard is being attacked. This study presents an FPGA implementation of the Serpent algorithm, the design is focused on the area rather than throughput thus iterative looping architecture is suggested. It is implemented on the target device Xilinx Virtex-6 xc6vlx195t-3ff1156 using ISE design suite 14.7. The design achieved a maximum frequency of 111.757 MHz providing 0.447 Gbit/sec of throughput.