Abstract: Memory ciphering system is a mechanism to secure the data in non-volatile memories of the system using standard encryption module and other security protections. Memory ciphering system in a smart card consists of three important units. Advanced Encryption Standard (AES) cipher, Random Number Generator (RNG) and Scrambler/Descrambler. It is built inside the Memory Management Processing Unit (MMPU) for securing data transactions with the smart card memories. This study presents the results of a comparative study performed between Xilinxs and Intels (previously Altera) Advanced RISC Machines (ARM) based Field Programmable Gate Array (FPGA) in prototyping smart card design with memory ciphering system. The smart card design is implemented in Xilinxs Zynq-7000 XC7020-1-CLG484 and Intels Cyclone V System-on-a-Chip (SoC) 5 CSEMA 5 F 31 C6N devices. The objective of this study is to identify the optimum FPGA platform for the prototype. The comparative study between the two ARM-based FPGA implementations is explained in terms of logics utilization and time requirements. The memory ciphering system in the smart card is capable to complete in 40 nsec that is a single CPU clock cycle of the smart card. Results obtained showed that the implementation in the Intel Cyclone V SoC has the least utilized logics and the highest maximum frequency which are 8.313 slices and 195 MHz, respectively. Since, the smart card prototyping in FPGA is the prerequisite for its Application Specific Integrated Circuit (ASIC) implementation, findings from this study serve as a good reference for enhancing secure smart card performance especially for logic optimization in ASIC.
Wira Firdaus Yaakob, Hazleen Aris and Jahariah Sampe, 2018. A Comparative Study of Smart Card Design with Memory Ciphering System on Arm-Based FPGA. Journal of Engineering and Applied Sciences, 13: 2638-2646.