Authors : Mohammed Darmi, Lekbir Cherif, Jalal Benallal, Rachid Elgouri and Nabil Hmina
Abstract: Power consumption is one of the major criteria of an Integrated Circuit (IC) and becomes more important than performance and surface in some applications. Therefore, it is necessary to find new techniques to reduce the power consumed by an IC. This study presents two power-aware techniques: Toggle rate and capacitance-toggle rate weighting which aims to reduce the switching power of nets at the placement stage. These techniques drive the placement engine to reduce the wire length of critical power nets by placing their relative cells close to each other. For an optimal solution, the weighting is applied only on power critical nets that consume more than 80% of the total power in the connection. Experimental results on nine IC industrial designs show an average improvement of 11.8% in total net power and 3.7% of total consumed power.
Mohammed Darmi, Lekbir Cherif, Jalal Benallal, Rachid Elgouri and Nabil Hmina, 2019. Capacitance-Toggle Rate Weighting to Optimize Switching Power at Placement Stage of VLSI Conception. Journal of Engineering and Applied Sciences, 14: 3243-3249.