Journal of Engineering and Applied Sciences

Year: 2018
Volume: 13
Issue: 9
Page No. 2767 - 2772

Design and Implementation of Low Power Clock Gating Technique in 16 bit ALU Circuit

Authors : Hussein Shakor Mogheer, Adham Hadi Saleh and Abbas Salman Hameed

References

Aanandam, S.K., 2007. Deterministic clock gating for low power VLSI design. Ph.D Thesis, Department of Electronics & Communication Engineering, National Institute of Technology, Rourkela, India.

Brynjolfson, I. and Z. Zilic, 2000. Dynamic clock management for low power applications in FPGAs. Proceedings of the IEEE 2000 International Conference on Custom Integrated Circuits (CICC), May 24, 2000, IEEE, Orlando, Florida, USA., pp: 139-142.

Chaudhary, H., N. Goyal and N. Sah, 2015. Dynamic power reduction using clock gating: A review. Intl. J. Electron. Commun. Technol., 6: 22-26.
Direct Link  |  

Czapski, P.P. and A. Sluzek, 2007. Power optimization techniques in FPGA devices: A combination of system-and low-levels. Intl. J. Electr. Comput. Syst. Eng., 1: 148-154.
Direct Link  |  

Dev, M.P., D. Baghel, B. Pandey, M. Pattanaik and A. Shukla, 2013. Clock gated low power sequential circuit design. Proceedings of the IEEE Conference on Information and Communication Technologies, April 11-12, 2013, JeJu Island, pp: 440-444.

Kathuria, J., M. Ayoubkhan and A. Noor, 2011. A review of clock gating techniques. MIT. Intl. J. Electron. Commun. Eng., 1: 106-114.
Direct Link  |  

Sahni, K., K. Rawat, S. Pandey and Z. Ahmad, 2015. Power optimization of communication system using clock gating technique. Proceedings of the 5th International Conference on Advanced Computing and Communication Technologies (ACCT’15), February 21-22, 2015, IEEE, Haryana, India, ISBN:978-1-4799-8488-6, pp: 375-378.

Soni, D.K. and A. Hiradhar, 2015. A review on existing clock gating. Intl. J. Comput. Sci. Mobile Comput., 4: 371-382.
Direct Link  |  

Zhang, Y., J. Roivainen and A. Mammela, 2006. Clock-gating in FPGAs: A novel and comparative evaluation. Proceedings of the 9th Euromicro International Conference on Digital System Design Architectures, Methods and Tools, August 30-September 1, 2006, IEEE, Dubrovnik, Croatia, pp: 584-590.

Zhao, P., Z. Wang and G. Hang, 2010. Power optimization for VLSI circuits and systems. Proceedings of the 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT’10), November 1-4, 2010, IEEE, Shanghai, China, ISBN:978-1-4244-5797-7, pp: 639-642.

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