Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 17
Page No. 3196 - 3204

Fast Architecture Multiplier Less Based DWT

Authors : A. Akilandeswari and P. Sakthivel

Abstract: Now a days, there is very much use of multimedia technologies, so there is need of improvement in the image compression technique in terms of performance and also the new features. Due to advantages of the discrete wavelet transform over the traditional transforms, it became very popular in the area of image processing. A Fast Architecture (FA) for 2-D Discrete Wavelet Transform (DWT) with use of improved Lifting scheme is presented in this study. Likewise embedded decimation technique used for the 1-D Discrete Wavelet Transform (DWT), pipelined and parallel structured 2-D DWT proposed in this study. In this study, we have proposed the multiplier less pipeline method for DWT. The advantage of this technique is that it does maximum utilization of the designed hardware. It does the J levels of decomposition when input image of size NxN given in an around 2N2 (1-4raise to-j)/3 of clock cycles. This method is called as Fast Architecture (FA). Using this technique throughput rate, output latency, etc are improved at the cost of some additional hardware. So, proposed architecture is better alternative for high speed applications.

How to cite this article:

A. Akilandeswari and P. Sakthivel, 2016. Fast Architecture Multiplier Less Based DWT. Asian Journal of Information Technology, 15: 3196-3204.

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