Abstract: In order to shield memories against MCUs (Multiple Cell Upset) as SEUs (Single Event Upset) an advanced fault detecting and correcting codes called Low Density Parity Check (LDPC) codes is devised. It is found to correct one fault per word which belongs to the family of the majority logic decoding recently projected for Ternary Content Addressable Memory (TCAM) memory application and Difference Set Cyclic Codes (DSCC). ML (Majority Logic) decodable codes measure appropriate Ternary Content Addressable Memory (TCAM) applications because of their capability to correct an outsized variety of faults. The present parity check algorithm on ML decodable codes optimizes the chip area overhead. But our projected idea for fault diagnosis algorithm makes significant Ternary Content Addressable Memory (TCAM) space overhead. Compared with the prevailing technique used for scaling back the decoding time through hybrid codes, our proposed technique offers promising choice for (TCAM) applications. It will reduce extra overhead in decoding algorithms specially designed for TCAM applications which intend to enhance the error-detection and correction capabilities. HDL (Hardware Description Language), simulation and synthesis results are enclosed herewith show that the projected techniques will be expeditiously analyzed in Spartan 6 low power FPGA for analyzing parameter in terms of TCAM, timing and power.
K. Mathan, T. Ravichandran, D. Mahesh Kumar and R. Kannusamy, 2016. Fault Diagnosis in Ternary Content Addressable Memory with Secured and Improved Decoding Algorithm. Asian Journal of Information Technology, 15: 3366-3375.