Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 24
Page No. 5181 - 5186

Evaluations of Cache Coherence Protocols in Terms of Power and Latency in Multiprocessors

Authors : Babak Aghaei and Negin Zaman-Zadeh

Abstract: The shared memory multiprocessors suffer with significant problem of accessing shared resources in a shared memory it will result in longer latencies. Consequently, the performance of the system will get affected. With the object of solving the problem of increased access latency due to large number of processors with shared memory, Cache is being used. Every processor has its own private cache, now they can update or access the data comfortably but again it leads to another serious issue i.e., cache coherency. The magnitude of the potential performance difference between the various cache coherency approaches indicates that the choice of coherence solution is very important in the design of an efficient shared-bus multiprocessor, since it may limit the number of processors in the system. In this paper we evaluate a typical multiprocessor system in terms of power and latency with different cache coherence protocols where GEM5 simulator is used. The traffic is generated with five injection rates (0.1, 0.2, 0.3, 0.4 and 0.5). Power and latency analyzing figures are made up and appeared in experimental result. The result shows MOESI_CMP_token has maximum latency and power consumption.

How to cite this article:

Babak Aghaei and Negin Zaman-Zadeh, 2016. Evaluations of Cache Coherence Protocols in Terms of Power and Latency in Multiprocessors. Asian Journal of Information Technology, 15: 5181-5186.

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