Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 5
Page No. 955 - 960

An Analog Low Power VLSI Implementation of Artificial Neural Network Architecture

Authors : S. Arumugam and N. Rajeswaran

Abstract: All the modern technologies in digital systems are slowly converting in to the analog implementation especially, for the fault tolerance and low power consumption. But, the analog implementation of parallel computation with ANN (Artificial Neural Network) in real time implementation is not an easy task in all aspects. This study mainly focuses on the implementation of Neural Network Architecture (NNA) with on chip learning in analog VLSI (Very Large Scale Integration). Back Propagation Neural network (BPN) algorithm is designed and simulated in analog domain by using tanner EDA tool.

How to cite this article:

S. Arumugam and N. Rajeswaran, 2016. An Analog Low Power VLSI Implementation of Artificial Neural Network Architecture. Asian Journal of Information Technology, 15: 955-960.

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