Asian Journal of Information Technology

Year: 2017
Volume: 16
Issue: 9
Page No. 691 - 698

A Low Offset Low Power Dynamic Comparator for High-Speed Applications in 65 nm Technology

Authors : Arumugam Sathishkumar and Siddhan Saravanan

Abstract: The study presents a design of low noise, stacking reduction, low power and low voltage double tail comparator for high speed application. The comparator design occupies less area and is suitable for the input stage of a Flash ADC. The dynamic comparator proposed in this project not only eliminates the stacking issue related with the convential comparator but reduces the offset noise further. The need for low noise, low-power, area efficient and high speed flash adcs required in many application today made the work to progress in designing a comparator for analog-to-digital converter. In this study, the analysis and design of new dynamic comparator is proposed where the circuit of a conventional doubletail comparator is modified. The regenerative feedback is strengthened to reduce the delay time.The rail to rail output swing is also improved by 99% of V . DD The simulation results in a 65 nm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator is increased to 2.2 and 3.5 GHz at supply voltages of 0.6 and 1 V. The simulation is carried out using predictive technology model for 65 nm in HSPICE.

How to cite this article:

Arumugam Sathishkumar and Siddhan Saravanan, 2017. A Low Offset Low Power Dynamic Comparator for High-Speed Applications in 65 nm Technology. Asian Journal of Information Technology, 16: 691-698.

Design and power by Medwell Web Development Team. © Medwell Publishing 2022 All Rights Reserved