Authors : Faez F. Shareef , Ashwaq Talib Hashim and Waleed F. Shareef
Abstract: This study presents the implementation of RC6 Block cipher that involve encryption and decryption on FPGA Virtex II device with highly compact architecture through reuse the same units for the identical operation in both algorithms. The proposed design also analyzes the cipher mathematical operation to fit it into FPGA available resources.
Faez F. Shareef , Ashwaq Talib Hashim and Waleed F. Shareef , 2008. Compact Hardware Implementation of FPGA Based RC6 Block Cipher. Journal of Engineering and Applied Sciences, 3: 598-601.