Authors : A. Murali, K. Hari Kishore and D. Venkat Reddy
Abstract: To overcome the lack of observability in FPGA-based prototypes, trace-buffer insertion plays an important role in the design. But it also has a disadvantage of which it leads to the recompilation of the entire system. In this study, we introduce how the incremental techniques are used to discard the necessity of recompilation process on the circuit design and also we propose the CAD optimizations to improve the special features, routing capacity and minimizing the delay impacts. The use of these technique implementations in this circuitry, fastens the magnitudes than a full compilation. In this scenario, the incremental trace insertion is notable as higher as 98 times faster than a full compilation of the design and 25% of the memory capacity is used for tracing. The incremental circuits are more helpful for the designers only to modify by inserting the trigger circuitry rather than compiling the entire design.
A. Murali, K. Hari Kishore and D. Venkat Reddy, 2016. Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process. Journal of Engineering and Applied Sciences, 11: 2643-2650.