Authors : Shilpa K. Gowda, K.R. Rekha and K.R. Nataraj
Abstract: With the increase in demand for on chip networking, it has become very much necessary to design an architecture that will provide the solution to communication interfaces, low chip cost, guarantee the flexibility and high quality of service to the network. To address the above-mentioned requirements we proposed an architecture that is dynamically configure itself with respect to hardware modules such as routers, packet based switch and data packet size by changing the communication conditions and its requirements at rum time. The design is based on FPGA based digital design and incorporates routing algorithm such as x-y routing. We have built a novel hexagonal node pattern to improve the communication performance. The developed node has 6 ports architecture that is far superior to the persisting node architecture. The structure also has capability to increase communication capacity by 50%. The proposed architecture is capable of overcoming the drawbacks of popular interconnection using bus-based design which is most commonly used in FPGA based architecture developed on dynamic reconfiguration. It has been observed that the node utilizes very less area of just 15% of the available area on chip. We have also achieved reasonable low latency of just 14 clocks for the data to appear at the output node once applied at the input of the architecture. The design is have a high data throughput due to low time period of just 10 nsec. The overall design of the network is much more efficient as it has deadlock free architecture with ads up to the advantages of the design. As there is lot of on-chip space available the design can further be modified for checking different routing algorithm such as shortest path to make the network more efficient also the design can be improved by testing the same for more numbers of nodes.
Shilpa K. Gowda, K.R. Rekha and K.R. Nataraj, 2017. FPGA Based NoC with Deadlock Free Routing in Mesh Networks Using Hexagonal Nodes. Journal of Engineering and Applied Sciences, 12: 8046-8051.