Authors : Hyun-Chang Lee and Jong-Eon Lee
Abstract: Digital logic lab-unit plays an important role in electrical engineering education. However, conventional logic level circuit in logic lab is too easy to break down such as surge voltage, wire disconnection and ESD (Electro Static Discharge). In this study, disadvantages of conventional logic level display circuit in logic lab-unit were investigated and an improved logic level display circuit is proposed by both simple hardware circuit and software components with microprocessor. Hardware is constructed with a voltage pre-scaler and a limiter, its output supplied to analog-digital Converter of the microprocessor. In order to verify the performance of the proposed method, experimental circuits were set and the operating conditions were tested. It operates normally from minus input voltage to over voltage. In addition, the logic state is displayed in four stages of open load, logical-low, logical-high and over voltage. The hysteresis characteristics are realized to overcome instability of transition and verified it through experiments. The proposed method can protect against the voltage exceeding the allowable input voltage and it can also detect the input state. Especially, disconnection of wire can be detected by proposed logic level display circuit, so that, trials and errors are reduced.
Hyun-Chang Lee and Jong-Eon Lee, 2018. A Study on the Distinction Circuit of Logic Input-Level for Digital Logic Lab-Unit. Journal of Engineering and Applied Sciences, 13: 3020-3025.