Authors : Shashikanth Reddy, U. Somanaidu, D. Khalandar Basha and D.M.K. Chaitanya
Abstract: The purpose of this research is to analysis and design of single rail domino logic full adder with static and dynamic logic styles. In the research we are going to explain the five different logic styles with XOR/XNOR gates is the gate is the most fundamental gate in the adder circuit namely full static CMOS logic, Complementary Pass-Transistor Logic (CPL) and dual-rail Domino dynamic logic in compare with single-rail Domino dynamic logic are implemented. Proposed adder is implemented with 12 transistor knows as single rail Domino logic circuit. Proposed system is designed in cadence virtuoso tool simulations and calculation of power and delay calculated in 45 nm technology with power supply and voltage across 1.0 V) at different temperatures.
Shashikanth Reddy, U. Somanaidu, D. Khalandar Basha and D.M.K. Chaitanya, 2018. Low Power Single-Rail Domino Logic Full Adder Design. Journal of Engineering and Applied Sciences, 13: 8167-8174.