Authors : Abhishek Jain and Richa Gupta
Abstract: In semiconductor industry, image processing algorithms are developed and evaluated using software models (‘C’/MATLAB) before actual implementation of RTL. After the evaluation of the algorithm, software models are used as a golden reference model for the RTL development of the image processing algorithms. In this study, we are describing the novel black and white area preserving salt and pepper noise removal algorithm and its RTL implementation using Verilog language. SystemVerilog UVM based verification environment of salt and pepper noise removal RTL design is developed. Quality of different image denoising algorithms is quantitatively measured by different parameters, namely Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Structural Similarity Index (SSIM) and Multi Scale Structural Similarity Index (MS-SSIM). Time complexity is measured by Big O notation and stopwatch timer. The main motivation behind this work is to propose best efficient black and white area preserving salt and pepper noise removal algorithm, its RTL implementation and development of efficient functional verification framework of salt and pepper noise removal RTL design. The proposed algorithm gives better MSE, PSNR, SSIM and MS-SSIM results. Time taken by proposed algorithm is not less than other existing algorithms but it is acceptable as Big O notation is same for other algorithms.
Abhishek Jain and Richa Gupta, 2019. Development and Verification of Novel Black and White Area Preserving Salt and Pepper Noise Removal Image Processing Design. Journal of Engineering and Applied Sciences, 14: 1828-1839.