Abstract: In this research, researchers introduce a low power and high performance serial on-chip communication link based on innovative design techniques and its design methodologies are presented in this research work. The proposed semi-serial link is designed using high speed serialization/deserialization and multi-orthogonal encoding techniques. The link also employs acknowledgement scheme to maintain the high speed data intake from the serializer. The proposed semi-serial link is analyzed and compared with bit-serial and fully bit-parallel links for 64 bit data communications. The results show that the proposed semi-serial link dissipates the lowest energy per bit compared to fully bit-parallel links at the same time achieving the same performance. The proposed semi-serial on-chip is designed and simulated in Xilinx Project navigator and tested on various FPGA devices using 90 nm CMOS technology.