Abstract: In vedic mathematics of the sixteen algorithms, Urdhva Tiryakbhyam is identified as one among the efficient algorithms for multiplication in terms of delay, power and area. In this study, a parallel MAC unit has been developed which employs compressor based Urdhva Tiryakbhyam multiplier for its operation. Transistor level power optimization is realized by Gate Diffusion Input (GDI) Technique using Synopsys HSPICE. The main advantage of the proposed technique is use of less number of transistors, result in reduced power consumption. The experimental results indicate an absolute reduction in total power consumption by 39 and 34.2% for 4-bit and 8-bit MAC, respectively when compared to standard CMOS technique.