Abstract: Dynamically, reconfigurable architectures have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions efficiently. Multipliers are basic functional units in today’s digital signal processing and digital image processing algorithms. Multipliers have large area, long latency and consume more power. Many researchers have been trying to design multiplier architectures which offer the design targets such as high speed, low power consumption and less area. Several multiplier architectures and their performance characteristics have been analyzed and compared in this study. Then, a reconfigurable architecture which consists of an array of two different processing elements with suitable interconnects has been proposed for an efficient implementation of signal processing algorithms. From the results, it has been identified that the proposed reconfigurable architecture provides an area efficiency of 37% more than the conventional reconfigurable multiplier architecture.