Abstract: Power is a major concern in the design and implementation of sequential circuits. Various attempts were made in the past to optimize power consumption values in the sequential circuits such as flip flops. Enhanced multi threshold CMOS is adopted in this work, which yielded best results for D flip-flop in terms of power consumption. The results are also examined for 180, 90 and 45 nm technology and the performance of the circuit is analyzed. A comprehensive analysis is carried out in terms of performance parameters as power consumption, leakage current and delay. The EMTCMOS Flip Flop is also used to design the ripple counter circuit and the performance was analyzed. However, this design is analyzed for only 90 nm technology. This research is carried on Cadence Virtuoso tool at 180, 90 and 45 nm technology.