Abstract: This study presents the architecture of FPGA-based Sigma-Delta ADC (SD ADC) utilizing higher integration of noise-shaper modulator and a sinc filter. The noise-shaper modulator employed the Low Voltage Differential Signaling (LVDS) as a comparator for maximum integration. Shaping the quantization noise to higher frequencies is achieved by placing the integrator block of Sigma-Delta Modulator (SDM) across the analog input signal results in lowering the noise level in the bandwidth of interested. Therefore, higher Signal to Noise and Distortion (SINAD) and Effective Number of Bits (ENOB) is able to be achieved with less filter and decimation stage complexity. Sinc filter is chosen as hardware efficient digital filter and decimation stage. Both the integrated noise shaper modulator and the sinc filter on the FPGA results in higher SINAD and ENOB. The architecture is designed and simulated on Quartus II. The SD ADC is implemented on Altera DE-I Cyclone II FPGA board for 8 bit resolution. The results achieved 45.14 peak SINAD and 7.21 bits peak ENOB over a 10 kHz signal bandwidth.