Abstract: In this study, an efficient adder for reducing the delay of the circuit is designed. Here, designed a modified SQRT-CSLA for high speed applications. BEC overcome the carry propagation delay of the CSLA adder and also it takes small number of gates to implement the design. In the circuit Ripple Carry Adder (RCA) is changed to BEC for achieving the efficiency the design is done by using verilogHDL and verifies the simulation results by ModelSim 6.3c. Finally the designed adder is compared with conventional carry select adder for differentiate the adder performance. The designed adder is applied into the FIR filter for high speed application.