Abstract: This research study proposes a novel architecture for a memory based pipelined fast fourier transform for a complex-valued signals which is based on radix-2 Decimation-In-Frequency (DIF) algorithm. A method of stage partition for a Complex Fast Fourier Transform (CFFT) to minimize the computation clock cycles and maximize the utilization of the Processing Element (PE) is proposed. In addition to this the CFFT architecture can also support more PEs in two dimensions as well. As compared to the previous research, the suggested CFFT processors have fewer computation cycles and lower hardware usage. ISE Xilinx 12.2 tool in verilog language has been utilized for designing and simulation.