Abstract: Low power SRAM array is fundamental to organize substantial reliability and prolonged battery life for portable application. Since, charging/discharging enormous bit lines capacitance consume large portion of power, new SRAM design is proposed to lessen the power consumption and access delay for read/write operation. The proposed 11T cell contains two transistors in the feedback path of the respective inverter to minimize the write power consumption. Cell is simulated in terms of speed, power and stability. The simulated results show that the read and write power of the 11T SRAM cell is reduced up to 49 and 80% at 0.7 V, respectively and cell achieves 2.5× higher Static Noise Margin (SNM) compared to the conventional 6T SRAM cell. The designed cell can be utilized in mobile appliances even in worse temperature state with lower power consumption.