Abstract: Design for test engineers has to group memories for BIST implementation. But there are various problems involved during memory grouping such as number of memories are increasing day by day and DFT engineers spends lots of time on grouping memories for BIST structure. Also, the memories may have different frequency of operation and the physical placement may also be different and scattered. This study presents an algorithm to group the memory in an efficient way such that it reduces the effort of memory grouping for BIST structure and BIST can support the grouping. Also, it take care the power during memory BIST operation.