Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 13
Page No. 2162 - 2166

Scheduled Progressive Edge Growth LDPC Encoder with Minimum Trapping Set

Authors : A. Anand and P. Senthilkumar

References

Gallager, R., 1962. Low-density parity-check codes. IRE. Trans. Inf. Theory, 8: 21-28.
CrossRef  |  Direct Link  |  

Hu, X.Y., E. Eleftheriou and D.M. Arnold, 2005. Regular and irregular progressive edge-growth tanner graphs. IEEE. Trans. Inf. Theory, 51: 386-398.
CrossRef  |  Direct Link  |  

Ramamoorthy, A. and R. Wesel, 2004. Construction of short block length irregular low-density parity-check codes. Proceedings of the 2004 IEEE International Conference on Communications, June 20-24, 2004, IEEE, Paris, France, ISBN: 0-7803-8533-0, pp: 410-414.

Richardson, T., 2003. Error floors of LDPC codes. Proceedings of the Annual Allerton Conference on Communication Control and Computing, October 1-3, 2003, Qualcomm Flarion Technologies, Bedminster, New Jersey, pp: 1426-1435.

Richter, G., 2006. Finding small stopping sets in the Tanner graphs of LDPC codes. Proceedings of the Turbo Codes and Related Topics 6th International ITG-Conference and 4th International Symposium on Source and Channel Coding (TURBOCODING), April 3-7, 2006, IEEE, Munich, Germany, ISBN: 978-3-8007-2947-0, pp: 1-5.

Sharon, E. and S. Litsyn, 2008. Constructing LDPC codes by error minimization progressive edge growth. IEEE. Trans. Commun., 56: 359-368.
CrossRef  |  Direct Link  |  

Tian, T., C.R. Jones, J.D. Villasenor and R.D. Wesel, 2004. Selective avoidance of cycles in irregular LDPC code construction. IEEE. Trans. Commun., 52: 1242-1247.
CrossRef  |  Direct Link  |  

Zheng, X., F.C. Lau and K.T. Chi, 2010. Constructing short-length irregular LDPC codes with low error floor. IEEE. Trans. Commun., 58: 2823-2834.
CrossRef  |  Direct Link  |  

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