References

Cho, K.J., K.C. Lee, J.G. Chung and K.K. Parhi, 2004. Design of low-error fixed-width modified booth multiplier. IEEE. Trans. Very Large Scale Integr. VLSI. Syst., 12: 522-531.
CrossRef  |  Direct Link  |  

Choi, J., J. Jeon and K. Choi, 2000. Power minimization of functional units partially guarded computation. Proceedings of the 2000 International Symposium on Low Power Electronics and Design, July 25-27, 2000, ACM, Rapallo, Italy, ISBN:1-58113-190-9, pp: 131-136.

Chowdhury, M.H., J. Gjanci and P. Khaled, 2008. Innovative power gating for leakage reduction. Proceedingd of the 2008 IEEE International Symposium on Circuits and Systems, May 18-21, 2008, IEEE, Chicago, USA, ISBN:978-1-4244-1683-7, pp: 1568-1571.

Huang, Z. and M.D. Ercegovac, 2005. High-performance low-power left-to-right array multiplier design. IEEE Trans. Comput., 54: 272-283.
CrossRef  |  Direct Link  |  

Kim, S. and K. Cho, 2010. Design of high-speed modified booth multipliers operating at GHz ranges. World Acad. Sci. Eng. Technol., 37: 1-4.
Direct Link  |  

Kuang, S.R., J.P. Wang and C.Y. Guo, 2009. Modified booth multipliers with a regular partial product array. IEEE. Trans. Circuits Syst. Express Briefs, 56: 404-408.
CrossRef  |  Direct Link  |  

Kuang, S.R., K.Y. Wu and K.K. Yu, 2013. Energy-efficient multiple-precision floating-point multiplier for embedded applications. J. Signal Process. Syst., 72: 43-55.
CrossRef  |  Direct Link  |  

Lim, Y.C., 1992. Single-precision multiplier with reduced circuit complexity for signal processing applications. IEEE Trans. Comput., 41: 1333-1336.
CrossRef  |  

Schulte, M.J. and E.E. Swartzlander, 1993. Truncated multiplication with correction constant [for DSP]. Proceedings of the Workshop on VLSI Signal Processing, October 20-22, 1993, IEEE, Austin, Texas, USA, ISBN:0-7803-0996-0, pp: 388-396.

Stevenson, D., 1981. A proposed standard for binary floating-point arithmetic. Comput., 14: 51-62.
CrossRef  |  Direct Link  |  

Tan, D., C.E. Lemonds and M.J. Schulte, 2009. Low-power multiple-precision iterative floating-point multiplier with SIMD support. IEEE. Trans. Comput., 58: 175-187.
CrossRef  |  Direct Link  |  

Thomas, M., 2014. Design and simulation of radix-8 booth encoder multiplier for signed and unsigned numbers. Int. J. Innov. Res. Sci. Technol., 1: 1-10.
Direct Link  |  

Tong, J.Y.F., D. Nagle and R.A. Rutenbar, 2000. Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE. Trans. Very Large Scale Integr. VLSI. Syst., 8: 273-286.
CrossRef  |  Direct Link  |  

Visalli, G. and F. Pappalardo, 2003. Low-power floating-point encoding for signal processing applications. Proceedings of the IEEE Workshop on Signal Processing Systems SIPS-2003, August 27-29, 2003, IEEE, Catania, Italy, ISBN:0-7803-7795-8, pp: 292-297.

Wang, L.R., S.J. Jou and C.L. Lee, 2008. A well-structured modified Booth multiplier design. Proceedings of the IEEE International Symposium on VLSI Design, Automation and Test VLSI-DAT-2008, April 23-25, 2008, IEEE, Taiwan, China, ISBN:978-1-4244-1616-5, pp: 85-88.

Wen, M.C., S.J. Wang and Y.N. Lin, 2005. Low power parallel multiplier with column bypassing. Proceedings of the IEEE International Symposium on Circuits and Systems, Volume 2, May 23-26, 2005, China, pp: 1638-1641.

Wires, K.E., M.J. Schulte and J.E. Stine, 2001. Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation. Proceedings of the 2001 International Conference on Computer Design ICCD-2001, September 23-26, 2001, IEEE, Allentown, Pennsylvania, USA, ISBN:0-7695-1200-3, pp: 497-500.

Wu, K.Y., S.R. Kuang and K.K. Yu, 2013. An exact method for estimating maximum errors of multi-mode floating-point iterative booth multiplier. Int. J. Comput. Sci. Eng., 8: 306-315.
CrossRef  |  Direct Link  |  

Yeh, W.C. and C.W. Jen, 2000. High-speed booth encoded parallel multiplier design. IEEE Trans. Comput., 49: 692-701.
Direct Link  |