References

Akhter, S. and S. Chaturvedi, 2014. Hdl based implementation of NxN bit serial multiplier. Proceedings of the International Conference on Signal Processing and Integrated Networks, February 20-21, 2014, India, pp: 470-474.

Almiladi, A., M.K. Ibrahim, M. Al Akidi and A. Aggoun, 2007. High-performance scalable bidirectional mixed radix-2ⁿ serial-serial multipliers. IET Comput. Digital Techniques, 1: 632-639.
CrossRef  |  Direct Link  |  

Doroz, Y., E. Ozturk and B. Sunar, 2014. A million-bit multiplier architecture for fully homomorphic encryption. Microprocessors Microsyst., 38: 766-775.
CrossRef  |  Direct Link  |  

Dorrigiv, M. and G. Jaberipur, 2014. Low area/power decimal addition with carry-select correction and carry-select sum-digits. Integration VLSI J., 47: 443-451.
CrossRef  |  Direct Link  |  

Gao, S., D. Al-Khalili and N. Chabini, 2009. Efficient scheme for implementing large size signed multipliers using multigranular embedded DSP blocks in FPGAs. Int. J. Reconfigurable Comput., Vol. 2009. 10.1155/2009/145130

Haynes, S.D., A.B. Ferrari and P.Y. Cheung, 1999. Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. Proceedings of the IEEE Custom Integrated Circuits, May 16-19, 1999, San Diego, CA., pp: 191-194.

Jevtic, R. and C. Carreras, 2010. Power estimation of embedded multiplier blocks in FPGAs. IEEE Trans. Very Large Scale Integration (VLSI) Syst., 18: 835-839.
CrossRef  |  Direct Link  |  

Kanhe, A., S.K. Das and A.K. Singh, 2012. Design and implementation of floating point multiplier based on Vedic multiplication technique. Proceedings of the International Conference on Communication, Information and Computing Technology, October 2012, Mumbai, India, pp: 1-4.

Koutroumpezis, G., K. Tatas, D. Soudris, S. Blionas, K. Masselos and A. Thanailakis, 2002. Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. In: Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream, Glesner, M., P. Zipf and M. Renovell (Eds.). Springer, New York, pp: 1027-1036.

Liu, C., J. Han and F. Lombardi, 2014. A low-power, high-performance approximate multiplier with configurable partial error recovery. Proceedings of the Conference on Design, Automation and Test in Europe, March 24-28, 2014, Dresden, Germany -.

Mariammal, K., V. Rani, S.P. Joy and T. Kohila, 2013. Area efficient high speed low power multiplier architecture for multirate filter design. Proceedings of the International Conference on Emerging Trends in Computing, Communication and Nanotechnology, March 25-26, 2013, Tirunelveli, pp: 109-116.

Meher, M.R., C.C. Jong and C.H. Chang, 2011. A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters. IEEE Trans. Very Large Scale Integration (VLSI) Syst., 19: 1733-1745.
CrossRef  |  Direct Link  |  

Miyamoto, A., N. Homma, T. Aoki and A. Satoh, 2011. Systematic design of RSA processors based on high-radix Montgomery multipliers. IEEE Trans. Very Large Scale Integration (VLSI) Syst., 19: 1136-1146.
CrossRef  |  Direct Link  |  

Pekmestzi, K.Z., P. Kalivas and N. Moshopoulos, 2001. Long unsigned number systolic serial multipliers and squarers. IEEE Trans. Circ. Syst. II: Analog Digital Signal Process., 48: 316-321.
CrossRef  |  Direct Link  |  

Ramkumar, B. and H.M. Kittur, 2012. Low-power and area-efficient carry select adder. IEEE Trans. Very Large Scale Integr. Syst., 20: 371-375.
CrossRef  |  Direct Link  |  

Sriraman, L. and T.N. Prabakar, 2012. Design and implementation of two variable multiplier using KCM and Vedic mathematics. Proceedings of the 1st International Conference on Recent Advances in Information Technology, March 15-17, 2012, Dhanbad, pp: 782-787.

Xydis, S., G. Economakos, D. Soudris and K. Pekmestzi, 2011. High performance and area efficient flexible DSP datapath synthesis. IEEE Trans. Very Large Scale Integration (VLSI) Syst., 19: 429-442.
CrossRef  |  Direct Link  |