References

Abadal, S., M. Iannazzo, M. Nemirovsky, A. Cabellos-Aparicio and H. Lee et al., 2015. On the area and energy scalability of wireless network-on-chip: A model-based benchmarked design space exploration. IEEE. ACM. Trans. Netw., 23: 1501-1513.
CrossRef  |  Direct Link  |  

Agyeman, M.O., K.F. Tong and T. Mak, 2015. Towards reliability and performance-aware wireless network-on-chip design. Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS’15), October 12-14, 2015, IEEE, Amherst, Massachusetts, ISBN:978-1-4799-8631-6, pp: 205-210.

Devigo, R., L. Duenha, R. Azevedo and R. Santos, 2015. Multiexplorer: A tool set for multicore system-on-chip design exploration. Proceedings of the 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP’15), July 27-29, 2015, IEEE, Toronto, Canada, ISBN:978-1-4799-1925-3, pp: 160-161.

Duraisamy, K., Y. Xue, P. Bogdan and P.P. Pande, 2017. Multicast-aware high-performance wireless network-on-chip architectures. IEEE. Trans. Very Large Scale Integr. (VLSI) Syst., 25: 1126-1139.
CrossRef  |  Direct Link  |  

Kaya, S., S. Laha, A. Kodi, D. Ditomaso and D. Matolak et al., 2013. On ultra-short wireless interconnects for NoCs and SoCs: Bridging the ‘THz Gap’. Proceedings of the 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS’13), August 4-7, 2013, IEEE, Columbus, Ohio, USA., ISBN:978-1-4799-0066-4, pp: 804-808.

Laha, S., S. Kaya, D.W. Matolak, W. Rayess and D. DiTomaso et al., 2015. A new frontier in ultralow power wireless links: Network-on-chip and chip-to-chip interconnects. IEEE. Trans. Comput. Aided Des. Integr. Circuits Syst., 34 186 198-10.1109/TCAD.2014.2379640.

Liu, F., H. Gu and Y. Yang, 2012. DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip. Comput. Electr. Eng., 38: 270-281.
CrossRef  |  Direct Link  |  

Martin, G. and H. Chang, 2001. System-on-chip design. Proceedings of the 4th International Conference on ASIC, October 23-25, 2001, IEEE, Shanghai, China, pp: 12-17.

Mondal, H.K., S.H. Gade, M.S. Shamim, S. Deb and A. Ganguly, 2017. Interference-aware wireless network-on-chip architecture using directional antennas. IEEE. Trans. MultiScale Comput. Syst., 3: 193-205.
CrossRef  |  Direct Link  |  

Rezaei, A., F. Safaei, M. Daneshtalab and H. Tenhunen, 2014. HiWA: A hierarchical wireless network-on-chip architecture. Proceedings of the 2014 International Conference on High Performance Computing and Simulation (HPCS’14), July 21-25, 2014, IEEE, Bologna, Italy, ISBN:978-1-4799-5312-7, pp: 499-505.

Rezaei, A., M. Daneshtalab, D. Zhao, F. Safaei and X. Wang et al., 2015. Dynamic application mapping algorithm for wireless network-on-chip. Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP’15), March 4-6, 2015, IEEE, Turku, Finland, ISBN:978-1-4799-8491-6, pp: 421-424.

Sun, C., C.H.O. Chen, G. Kurian, L. Wei and J. Miller et al., 2012. DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. Proceedings of the 6th IEEE/ACM International Symposium on Networks on Chip (NoCS’12), May 9-11, 2012, IEEE, Copenhagen, Denmark, ISBN:978-1-4673-0973-8, pp: 201-210.

Yu, X., H. Rashtian, S. Mirabbasi, P.P. Pande and D. Heo, 2015. An 18.7-Gb/s 60-GHz OOK demodulator in 65-nm CMOS for wireless network-on-chip. IEEE. Trans. Circuits Syst. I Regul. Pap., 62: 799-806.
CrossRef  |  Direct Link  |