References

Al Faruque, M.A., T. Ebi and J. Henkel, 2012. AdNoC: Runtime adaptive network-on-chip architecture. IEEE Trans. Very Large Scale Integr. Syst., 20: 257-269.
CrossRef  |  

Anjum, S., E.U. Munir and M.W. Nisar, 2011. Simulation and performance evaluation of network on chip architectures and algorithms using CINSIM. J. Basic Applied Sci. Res., 1: 1594-1602.
Direct Link  |  

Babaei, S., M. Mansouri, B. Aghaei and A. Khadem-Zadeh, 2011. Online-structural testing of routers in network on chip. World Applied Sci. J., 14: 1374-1383.
Direct Link  |  

Bolotin, E., I. Cidon, R. Ginosar and A. Kolodny, 2004. QNoC: QoS architecture and design process for network on chip. J. Syst. Architecture, 50: 105-128.
CrossRef  |  

Choudhary, N., M.S. Gaur and V. Laxmi, 2011. Routing centric NoC design for high performance multimedia application. Int. J. Soft Comput. Eng., 1: 254-258.
Direct Link  |  

Daneshtalab, M., M. Ebrahimi, P. Liljeberg, J. Plosila and H. Tenhunen, 2012. Memory-efficient on-chip network with adaptive interfaces. IEEE Trans. Comput.-Aided Design Integ. Circuits Syst., 31: 146-159.
CrossRef  |  

DeOrio, A., D. Fick, V. Bertacco, D. Sylvester, D. Blaauw, J. Hu and G. Chen, 2012. A reliable routing architecture and algorithm for NoCs. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 31: 726-739.
CrossRef  |  

Jena, R.K., M.M. Aqel and P.K. Mahanti, 2011. Network-on-chip design space exploration: A PSO based integrated approach. Eur. J. Sci. Res., 64: 5-18.
Direct Link  |  

Ju, X. and L. Yang, 2011. NoC research and practice: Design and implementation of 2x4 2D-torus topology. Int. J. Inform. Technol. Comput. Sci., 4: 50-56.
Direct Link  |  

Kale, M.A. and M.A. Gaikwad, 2011. Design and analysis of on-chip router for network on chip. Int. J. Comput. Trends Technol., 9: 182-186.

Lee, K., S.J. Lee and H.J. Yoo, 2006. Low-power network-on-chip for high-performance SoC design. IEEE Trans. Very Large Scale Integr. Syst., 14: 148-160.
CrossRef  |  

Sivakamasundari, P., R. Sudha and S. Sasikala, 2011. Implementation of an effective router architecture for NoC on FPGA. Proceedings of the International Conference on Advanced Computer Technology, January 2-4, 2011, Bangalore, India -.