Authors : C.M.R. Prabhu, Prabu Mohan and P. Kesavan
Abstract: On-chip cache utilizes an enormous percentage of the entire chip region and spread with very fast rate in advanced technologies. Cell stability and low power SRAM are the major concerns and has become a crucial component in modern VLSI systems. Low power SRAM array is fundamental to organize substantial reliability and prolonged battery life for portable application. Since, charging/discharging enormous bit lines capacitance consume large portion of power, new SRAM design is proposed to lessen the power consumption and access delay for read/write operation. Single bit line technique performed in the proposed circuit lead to power consumption reduction during write operation about 79% and separate path used for read operation reduces the power consumption about 49.1% compared to 6T cell. Separate path during read operation and connecting/disconnecting the feedback path during write operation decrease the delay time and hence lessen the power consumption throughout read/write operation. The read/write stability is maintained in the proposed Novel 9T SRAM cell. The designed cell can be utilized in mobile appliances even in worse temperature state with lower power consumption.
C.M.R. Prabhu, Prabu Mohan and P. Kesavan, 2017. Novel Nine-Transistor (9T) SRAM for Read/Write Operation. Journal of Engineering and Applied Sciences, 12: 3793-3797.