References

Bos, H. and K. Huang, 2004. A network intrusion detection system on IXP1200 network processors with support for large rule sets. Technical Report 2004-02. http://www.cs.vu.nl/~herbertb/papers/trixpid.pdf.

Colajanni, M. and M. Marchetti, 2006. A parallel architecture for stateful intrusion detection in high traffic networks. Proceedings of the IEEE/IST Workshop on Monitoring, Attack Detection and Mitigation, September 28-29, 2006, Tuebingen, Germany, pp: 1-7.

Dimopoulos, V., I. Papaefstathiou and D. Pnevmatikatos, 2007. A memory-efficient reconfigurable Aho-Corasick FSM implementation for intrusion detection systems. Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, July 16-19, 2007, Samos, pp: 186-193.

Hu, Y., 2006. Embedded Network Processor based Parallel Intrusion Detection. In: Embedded Systems: Modeling, Technology and Applications, Hommel, G. and S. Huanye (Eds.). Springer, The Netherlands, ISBN-13: 9781402049330, pp: 93-100.

Pangrazio, G., 2008. Intel IXP network processor based intrusion detection. October 16, 2008, SANS Institute, USA. http://www.sans.org/reading-room/whitepapers/detection/intel-ixp-network-processor-based-intrusion-detection-32919.

Sommer, R., V. Paxson and N. Weaver, 2009. An architecture for exploiting multi-core processors to parallelize network intrusion prevention. Concurrency Computat.: Pract. Exp., 219: 1255-1279.
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