Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 6
Page No. 1090 - 1097

New Design for FIR Filter with Optimization of Speed and Power Using ASIC

Authors : Parvatham Vijay and Prabakaran Rajendran

References

Acharya, T. and P.S. Tsai, 2005. JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures. John Wiley and Sons, New Jersey, USA., ISBN: 9780471484226, Pages: 296.

Cheng, C. and K.K. Parhi, 2008. High-speed VLSI implementation of 2-D discrete wavelet transform. IEEE Trans. Signal Process., 56: 393-403.
CrossRef  |  

Cheng, C.C., C.T. Huang, C.Y. Cheng, C.J. Lian and L.G. Chen, 2007. On-chip memory optimization scheme for VLSI implementation of line-based two-dimentional discrete wavelet transform. IEEE Trans. Circuits Syst. Video Technol., 17: 814-822.
CrossRef  |  

Darji, A., S. Agrawal, A. Oza, V. Sinha, A. Verma, S.N. Merchant and A.N. Chandorkar, 2014. Dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform. IEEE Trans. Circuits Syst. II: Express Briefs, 61: 433-437.
CrossRef  |  

Hu, Y. and K.K. Parhi, 2013. Design and optimization of multiplierless FIR filters using sub-threshold circuits. J. Signal Process. Syst., 70: 259-274.
CrossRef  |  Direct Link  |  

Huang, C.T., P.C. Tseng and L.G. Chen, 2002. Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method. Proceedings of Asia-Pacific Conference on Circuits and Systems, Volume 1, October 28-31, 2002, Bali, Indonesia, pp: 363-366.

Huang, C.T., P.C. Tseng and L.G. Chen, 2004. Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Trans. Signal Process., 52: 1080-1089.
CrossRef  |  

Kotteri, K.A., A.E. Bell and J.E. Carletta, 2006. Multiplierless filter bank design: Structures that improve both hardware and image compression performance. IEEE Trans. Circuits Syst. Video Technol., 16: 776-780.
CrossRef  |  

Lai, Y.K., L.F. Chen and Y.C. Shih, 2009. A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform. IEEE Trans. Consum. Electron., 55: 400-407.
CrossRef  |  

Lee, D.U., L.W. Kim and J.D. Villasenor, 2012. Precision-aware self-quantizing hardware architectures for the discrete wavelet transform. IEEE Trans. Image Process., 21: 768-777.
CrossRef  |  

Liao, H., M.K. Mandal and B.F. Cockburn, 2004. Efficient architectures for 1-D and 2-D lifting-based wavelet transforms. IEEE Trans. Signal Process., 52: 1315-1326.
CrossRef  |  

Madishetty, S.K., A. Madanayake, R.J. Cintra, V.S. Dimitrov and D.H. Mugler, 2013. VLSI architectures for the 4-Tap and 6-Tap 2-D daubechies wavelet filters using algebraic integers. IEEE Trans. Circuits Syst. I: Regular Papers, 60: 1455-1468.
CrossRef  |  

Mallat, S.G., 1989. A theory for multiresolution signal decomposition: The wavelet representation. IEEE Trans. Pattern Anal. Mach. Intell., 11: 674-693.
CrossRef  |  Direct Link  |  

Marino, F., 2000. Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., 47: 1476-1491.
CrossRef  |  

Martina, M. and G. Masera, 2009. Multiplierless, folded 9/7-5/3 wavelet VLSI architecture. IEEE Trans. Circuits Syst. II: Express Briefs, 54: 770-774.
CrossRef  |  

Mohanty, B.K. and P.K. Meher, 2011. Memory efficient modular VLSI architecture for highthroughput and low-latency implementation of multilevel lifting 2-D DWT. IEEE Trans. Signal Process., 59: 2072-2084.
CrossRef  |  

Mohanty, B.K., A. Mahajan and P.K. Meher, 2012. Area- and power-efficient architecture for high-throughput implementation of lifting 2-D DWT. IEEE Trans. Circuits Syst. II: Express Briefs, 59: 434-438.
CrossRef  |  

Parhi, K.K. and T. Nishitani, 1993. VLSI architectures for discrete wavelet transforms. Very Large Scale Integr. Syst. IEEE. Trans., 1: 191-202.
CrossRef  |  Direct Link  |  

Parhi, K.K., 1999. VLSI Digital Signal Processing Systems: Design and Implementation. John Wiley and Sons, New Jersey, USA., ISBN: 9780471241867, Pages: 808.

Parvatham, N. and G. Seetharaman, 2012. A novel architecture for an efficient implementation of image compression using 2D-DWT. Proceedings of the 3rd International Conference on Intelligence system Modeling and Simulation, February 8-10, 2012, Kota Kinabalu, pp: 374-378.

Parvatham, V. and G. Seetharaman, 2014. Application specific integrated circuit implementation of multiplier free modified flipping architecture for image compression. Adv. Sci. Lett., 20: 2055-2059.
CrossRef  |  Direct Link  |  

Parvatham, V. and G. Seetharaman, 2014. Field programmable gate arrays implementation of multiplier free architecture for image compression. Adv. Sci. Lett., 20: 2050-2054.
CrossRef  |  Direct Link  |  

Sun, Q., J. Jiang, Y. Zhu and Y. Fu, 2013. Architecture for 1-D and 2-D discrete wavelet transform. Proceedings of the IEEE 21st Annual International symposium on Field Programmable Custom Computing Machines, April 28-30, 2013, Seattle, WA., pp: 81-84.

Tian, X., L. Wu, Y.H. Tan and J.W. Tian, 2010. Efficient multi-input/multi-output VLSI architecture for two-dimensional lifting-based discrete wavelet transform. IEEE Trans. Comput., 60: 1207-1211.

Wu, B.F. and C.F. Lin, 2005. A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec. IEEE Trans. Circ. Syst. Video Technol., 15: 1615-1628.
CrossRef  |  Direct Link  |  

Zhang, C., C. Wang and M.O. Ahmad, 2010. A pipeline VLSI architecture for high-speed computation of the 1-D discrete wavelet transform. IEEE Trans. Circuits Syst. I: Regular Papers, 57: 2729-2740.
CrossRef  |  

Zhang, C., C. Wang and M.O. Ahmad, 2012. A pipeline VLSI architecture for fast computation of the 2-D discrete wavelet transform. IEEE Trans. Circuits Syst. I: Regular Papers, 59: 1775-1786.
CrossRef  |  

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