References

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Goswami, K. and B. Pandey, 2014. LVCMOS Based thermal aware energy efficient vedic multiplier design on FPGA. Proceedings of the 2014 International Conference on Computational Intelligence and Communication Networks (CICN), November 14-16, 2014, IEEE, Bhopal, India, ISBN: 978-1-4799-6928-9, pp: 921-924.

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Thapliyal, H. and M.B. Srinivas, 2004. High speed efficient N x N Bit parallel hierarchical overlay multiplier architecture based on ancient Indian vedic mathematics. Enformatika Trans., 2: 225-228.
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Wallace, C.S., 1964. A suggestion for a fast multiplier. IEEE Trans. Electr. Comput., EC-13: 14-17.
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Xiaoping, C., H. Wei, C. Xin and W. Shumin, 2014. A new redundant binary partial product generator for fast 2n-Bit multiplier design. Proceedings of the 2014 IEEE 17th International Conference on Computational Science and Engineering (CSE), December 19-21, 2014, IEEE, Chengdu, China, ISBN: 978-1-4799-7980-6, pp: 840-844.