References

Balakrishnan, S., R. Rajwar, M. Upton and K. Lai, 2005. The impact of performance asymmetry in emerging multicore architectures. Proceedings of the 32nd Annual International Symposium on ACM SIGARCH Computer Architecture News, June 4-8, 2005, IEEE Computer Society, Washington, USA., ISBN:0-7695-2270-X, pp: 506-517.

Becchi, M. and P. Crowley, 2006. Dynamic thread assignment on heterogeneous multiprocessor architectures. Proceedings of the 3rd Conference on Computing Frontiers, May 3-5, 2006, ACM, New York, USA., ISBN:1-59593-302-6, pp: 29-40.

Fedorova, A., M. Seltzer and M.D. Smith, 2007. Improving performance isolation on chip multiprocessors via an operating system scheduler. Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, September 15-19, 2007, IEEE Computer Society, Washington, DC., USA., ISBN:0-7695-2944-5, pp: 25-38.

Fedorova, A., M. Seltzer, C. Small and D. Nussbaum, 2005. Performance of multithreaded chip multiprocessors and implications for operating system design. Proceedings of the Annual Conference on USENIX Annual Technical Conference, April 10-15, USENIX Association Berkeley CA, USA., pp: 26-26.

Hennessy, J.L. and D.A. Patterson, 2006. Computer Architecture: A Quantitative Approach. 4th Edn., Morgan Kaufmann, San Francisco, ISBN: 978-0-12-370490-0,.

Kumar, R., D.M. Tullsen, N.P. Jouppi and P. Ranganathan, 2005. Heterogeneous chip multiprocessors. Comput., 11: 32-38.
Direct Link  |  

Kumar, R., D.M. Tullsen, P. Ranganathan, N.P. Jouppi and K.I. Farkas, 2004. Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. ACM. SIGARCH. Comput. Archit. News, 32: 64-75.
CrossRef  |  Direct Link  |  

Kumar, R., K.I. Farkas, N.P. Jouppi, P. Ranganathan and D.M. Tullsen, 2003. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003, MICRO-36, December 3-5, 2003, IEEE, USA., ISBN: 0-7695-2043-X, pp: 81-92.

Kumar, S., C.J. Hughes and A. Nguyen, 2007. Carbon: Architectural support for fine-grained parallelism on chip multiprocessors. ACM. SIGARCH. Comput. Archit. News, 35: 35-173.
CrossRef  |  Direct Link  |  

Radhamani, A.S. and E. Baburaj, 2011. Implementation of Cache Fair Thread Scheduling for multi core processors using wait free data structures in cloud computing applications. Proceedings of the World Congress on Information and Communication Technologies, December 11-14, 2011, Mumbai, pp: 600-605.

Sherwood, T., E. Perelman, G. Hamerly and B. Calder, 2002. Automatically characterizing large scale program behavior. ACM. SIGOPS. Operating Syst. Rev., 36: 45-57.
CrossRef  |  Direct Link  |