References

Bartolozzi, C. and G. Indiveri, 2007. Synaptic dynamics in analog VLSI. Neural Comput., 19: 2581-2603.
CrossRef  |  Direct Link  |  

Chicca, E., D. Badoni, V. Dante, M.D. Andreagiovanni and G. Salina et al., 2003. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory. IEEE Trans. Neural Networks, 14: 1297-1307.
CrossRef  |  

Douglas, R., M. Mahowald and C. Mead, 1995. Neuromorphic analogue VLSI. Annu. Rev. Neurosci., 18: 255-281.
CrossRef  |  PubMed  |  Direct Link  |  

Hammouda, H.B., M. Mhiri, Z. Gafsi and K. Besbes, 2008. Neural-based models of semiconductor devices for SPICE simulator. Am. J. Applied Sci., 5: 385-391.
CrossRef  |  Direct Link  |  

Heittmann, A., 2000. An analog VLSI pulsed neural network for image segmentation using adaptive connection weights. Dresden University of Technology, Department of Electrical Engineering and Information Technology, Dresden, Germany.

Kuang, S.R. and J.P. Wang, 2007. Design of power efficient pipelined truncated multipliers with various output precision. IET Comput. Digital Tech., 1: 129-136.

Linares-Barranco, B., T. Serrano-Gotarredona and R. Serrano-Gotarredona, 2003. Compact low-power calibration mini-DACs for neural arrays with programmable weights. IEEE Trans. Neural Networks, 14: 1207-1216.
CrossRef  |  Direct Link  |  

Namba, K. and H. Ito, 2005. Design of defect tolerant Wallace multiplier. Proceedings of the 11th Pacific Rim International Symposium on Dependable Computing, December 12-14, 2005, Hunan, China, pp: 300-304.

Rajeswaran, N., T. Madhu and M. Suryakalavathi, 2013. VHDL synthesizable hardware architecture design of back propagation neural networks. Proceedings of the IEEE Conference on Information and Communication Technologies, April 11-12, 2013, JeJu Island, South Korea, pp: 445-450.

Rajeswaran, N., T. Madhu and M.S. Kalavathi, 2012. Fault diagnosis and testing of induction machine using Back Propagation Neural Network. Proceedings of the IEEE International Power Modulator and High Voltage Conference, June 3-7, 2012, San Diego, CA., USA., pp: 492-495.

Rao, P.V., C.P. Raj and S. Ravi, 2009. VLSI design and analysis of multipliers for low power. Proceedings of the 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, September 12-14, 2009, Kyoto, Japan, pp: 1354-1357.

Sjalander, M., M. Drazdziulis, P. Larsson-Edefors and H. Eriksson, 2005. A low-leakage twin-precision multiplier using reconfigurable power gating. Proceedings of the IEEE International Symposium on Circuits and Systems, Volume 2, May 23-26, 2005, Kobe, Japan, pp: 1654-1657.

Tu, J.H. and L.D. Van, 2009. Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers. IEEE Trans. Comput., 58: 1346-1355.
CrossRef  |  

Varghese, A., C.N. Marimuthu and P. Thangaraj, 2008. Low power high performance multiplier. Int. J. Soft Comput., 3: 412-420.
Direct Link  |  

Wang, A., B. Calhoun and A.P. Chandrakasan, 2006. Sub-Threshold Design for Ultra Low-Power Systems. Springer, New York, USA., ISBN-13: 978-0387335155, Pages: 209.

Zouyed, A. and A. Khoualdia, 2007. Contribution to definition of a structured design methodology of mixed circuit. Asia J. Inform. Technol., 6: 1218-1223.
Direct Link  |