Journal of Engineering and Applied Sciences

Year: 2016
Volume: 11
Issue: 12
Page No. 2643 - 2650

Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process

Authors : A. Murali, K. Hari Kishore and D. Venkat Reddy

References

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Hung, E. and S.J. Wilton, 2011. Speculative debug insertion for FPGAs. Proceeding of the 2011 21st International Conference on Field Programmable Logic and Applications, September 5-7, 2011, IEEE, Vancouver, BC, ISBN:978-1-4577-1484-9, pp: 524-531.

Hung, E. and S.J. Wilton, 2014. Incremental trace-buffer insertion for FPGA debug. IEEE. Trans. Very Large Scale Integr. Syst., 22: 850-863.
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Hung, E., F. Eslami and S.J. Wilton, 2013. Escaping the academic sandbox: Realizing VPR circuits on Xilinx devices. Proceeding of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, April 28-30, 2013, IEEE, Vancouver, Canada, ISBN:978-0-7695-4969-9, pp: 45-52.

Rose, J., J. Luu, C.W. Yu, O. Densmore and J. Goeders et al., 2012. The VTR project: Architecture and CAD for FPGAs from verilog to routing. Proceedings of the ACM-SIGDA International Symposium on Field Programmable Gate Arrays, February 22-24, 2012, ACM, California, USA., ISBN:978-1-4503-1155-7, pp: 77-86.

Rose, J., V. Betz and A. Marquardt, 1999. Architecture and Cad for Deep-Submicron Fpgas. Kluwer Academic Publishers, Norwell, Massachusetts,.

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