References

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Ahmad, N. and R. Hasan, 2013. A 0.8 V 0.23 nW 1.5 ns full-swing pass-transistor XOR gate in 130 nm CMOS. Act. Passive Electron. Components, Vol. 2013,

Ahmad, N. and S.R. Hasan, 2013. Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using novel XOR gate. Integr. VLSI. J., 46: 333-344.
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Babu, K.P., S.A. Basha and H. Devanna, 2014. Design of low power CMOS full subtractor. Intl. J. Innovative Sci. Eng. Technol., 1: 76-80.
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Baghel, S. and P.K. Rahi, 2015. Design and simulation of 2-bit full subtractor using various CMOS technologies. Intl. J. Eng. Tech. Res., 3: 209-212.
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Bazzazi, A., A. Mahini and J. Jelini, 2012. Low power full adder using 8T structure. Proceedings of the International Multi Conference on Engineers and Computer Scientist IMECS, March 14-16, 2012, IMECS, Hong Kong, ISBN:978-988-19251-9-0, pp: 1-5.

Chandra, K., R. Kumar, S. Uniyal and V. Ramola, 2015. A new design 6T full adder circuit using novel 2T XNOR gates. IOSR. J. VLSI. Signal Process., 5: 63-68.

Chowdhury, A.K., D.Y.W. Tan, S.L.B. Yew, G.L.C. Wyai and B. Madon et al., 2015. Design of full adder/subtractor using irreversible IG-A gate. Proceedings of the 2015 International Conference on Computer, Communications and Control Technology (I4CT), April 21-23, 2015, IEEE, Sibu, Malaysia, ISBN:978-1-4799-7953-0, pp: 103-107.

Verma, S., D. Kumar and G.K. Marwah, 2014. New high performance 1-bit full adder using domino logic. Proceedings of the 2014 International Conference on Computational Intelligence and Communication Networks (CICN), November 14-16, 2014, IEEE, Phagwara, India, ISBN:978-1-4799-6930-2, pp: 961-965.