Journal of Engineering and Applied Sciences

Year: 2017
Volume: 12
Issue: 4 SI
Page No. 6703 - 6709

Comparison of Modified Russian Peasant Multiplier based 12-Tap FIR Filter and Multiplierless 12-Tap FIR Filter

Authors : C. Uthaya Kumar and S. Kamalraj

References

Aksoy, L., P. Flores and J. Monteiro, 2014. A tutorial on multiplierless design of FIR filters: Algorithms and architectures. Circuits Syst. Signal Process., 33: 1689-1719.
Direct Link  |  

Dangra, K.H. and G.S. Gawande, 2016. Efficient design and implementation of multiplierless FIR filter. Proceedings of the 2016 International Conference on Computing Communication Control and automation (ICCUBEA’16), August 12-13, 2016, IEEE, Pune, India, ISBN:978-1-5090-3292-1, pp: 1-5.

Gowrishankar, V., D. Manoranjitham and P. Jagadeesh, 2013. Efficient FIR filter design using modified carry select adder and Wallace tree multiplier. Int. J. Sci. Eng. Technol. Res., 2: 703-711.
Direct Link  |  

Kadam, M., K. Sawarkar and S. Mande, 2015. Investigation of suitable DSP architecture for efficient FPGA implementation of FIR filter. Proceeding of the 2015 International Conference on Communication Information and Computing Technology (ICCICT’15), January 15-17, 2015, IEEE, Mumbai, India, ISBN:978-1-4799-5523-7, pp: 1-4.

Patel, S. and B. Mohanty, 2014. Area-delay-power efficient carry-select adder. IEEE Trans. Circ. Syst. II: Express Briefs, 61: 418-422.
CrossRef  |  Direct Link  |  

Patil, N., A. Joshi, N. Eskandari and T. Nikoubin, 2015. RCA with conditional BEC in CSLA structure for area-power efficiency. Proceedings of the 2015 IEEE 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT’15), July 13-15, 2015, IEEE, Denton, Texas, ISBN:978-1-4799-7985-1, pp: 1-4.

Prasad, G., V.S.P. Nayak, S. Sachin, K.L. Kumar and S. Saikumar, 2016. Area and power efficient carry-select adder. Proceedings of the 2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT’16), May 20-21, 2016, IEEE, Bangalore, India, ISBN:978-1-5090-0775-2, pp: 1897-1901.

Ramkumar, B. and H.M. Kittur, 2012. Low-power and area-efficient carry select adder. IEEE Trans. Very Large Scale Integr. Syst., 20: 371-375.
CrossRef  |  Direct Link  |  

Thingom, I. and P. Khundrakpam, 2016. FPGA implementation of FIR filter using RADIX-2 r. Proceedings of the 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET’16), March 23-25, 2016, IEEE, Chennai, India, ISBN:978-1-4673-9339-3, pp: 1524-1528.

Tyagi, A., 1993. A reduced-area scheme for carry-select adders. IEEE. Trans. Comput., 42: 1163-1170.
CrossRef  |  Direct Link  |  

Wallace, C.S., 1964. A suggestion for a fast multiplier. IEEE Trans. Electr. Comput., EC-13: 14-17.
CrossRef  |  

Waters, R.S. and E.E. Swartzlander, 2010. A reduced complexity wallace multiplier reduction. IEEE Trans. Comput., 59: 1134-1137.
CrossRef  |  Direct Link  |  

Design and power by Medwell Web Development Team. © Medwell Publishing 2024 All Rights Reserved