References

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Aly, R.E. and M.A. Bayoumi, 2007. Low-power cache design using 7T SRAM cell. IEEE. Trans. Circuits Syst. Express Briefs, 54: 318-322.
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Gopal, M., D.S.S. Prasad and B. Raj, 2013. 8T SRAM cell design for dynamic and leakage power reduction. Intl. J. Comput. Appl., 71: 43-48.
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Grossar, E., M. Stucchi, K. Maex and W. Dehaene, 2006. Read stability and write-ability analysis of SRAM cells for nanometer technologies. IEEE. J. Solid State Circuits, 41: 2577-2588.
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Liu, T.M., T.A. Lin, S.Z. Wang, W.P. Lee and J.Y. Yang et al., 2007. A 125$\ mu {\ hbox {W}} $, fully scalable MPEG-2 and H. 264/AVC video decoder for mobile applications. IEEE. J. Solid State Circuits, 42: 161-169.
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Prabhu, C.M.R. and A.K. Singh, 2009. A proposed SRAM cell for low power consumption during write operation. Microelectron. Intl., 26: 37-42.
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Seevinck, E., F.J. List and J. Lohstoh, 1987. Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circ., 22: 748-754.
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