References

Anonymous, 2004. Asynchronous FIFO v6.1. Xilinx, San Jose, California, USA. https://www.xilinx.com/support/documentation/ip_documentation/async_fifo.pdf

Anonymous, 2009. Tutorials on System verilog, Verilog, Open Vera, Verification, OVM, VMM, AXI, OCP. ASIC Company, Sydney, Australia. http://www.asicguru.com/

Anonymous, 2018. Asynchronous FIFO in virtex-FPGA’s. Australian Securities and Investments Commission, Sydney, Australia.

Bergeron, J., 2003. Writing Testbenches: Functional Verification of HDL Models. Springer, Berlin, Germany, ISBN:9781402074011, Pages: 475.

Bhasker, J., 1998. Verilog HDL Synthesis: A Practical Primer. Star Galaxy Publishing, Pennsylvania, USA., ISBN:9780965039154, Pages: 215.

Cummings, C.E. and P. Alfke, 2003. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons. In: Verilog HDL: A Guide to Digital Design and Synthesis, Palnitkar, S. (Ed.). Sun Microsystems Press Publisher, California‎, USA., pp: 1-18.

Han, H. and K.S. Stevens, 2009. Clocked and asynchronous FIFO characterization and comparison. Proceedings of the 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC’09), October 12-14, 2009, IEEE, Florianopolis, Brazil, ISBN:978-1-4577-0237-2, pp: 101-108.

Ramesh, G., V.S. Kumar and K.J. Reddy, 2012. Asynchronous FIFO design with gray code pointer for high speed AMBA AHB compliant memory controller. IOSR. J. VLSI Sig. Process., 1: 32-37.
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