References

Allred, D.J., H. Yoo, V. Krishnan, W. Huang and D.V. Anderson, 2005. LMS adaptive filters using distributed arithmetic for high throughput. IEEE Trans. Circuits Syst. I. Regul. Pap., 52: 1327-1337.
CrossRef  |  Direct Link  |  

Allred, D.J., W. Huang, V. Krishnan, H. Yoo and D.V. Anderson, 2004. An FPGA implementation for a high throughput adaptive filter using distributed arithmetic. Proceedings of the 12th International Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 20-23, 2004, IEEE, Napa, California, USA., pp: 324-325.

Chandekar, A.A. and M. Pawar, 2017. Delay and power optimized adaptive filter using distributed arithmetic. Proceedings of the 2017 International Conference on Electronics, Communication and Aerospace Technology (ICECA) Vol. 1, April 20-22, 2017, IEEE, Coimbatore, India, ISBN:978-1-5090-5685-9, pp: 256-261.

Guo, R. and L.S. DeBrunner, 2011. A novel adaptive filter implementation scheme using distributed arithmetic. Proceedings of the 2011 Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers (ASILOMAR), November 6-9, 2011, IEEE, Pacific Grove, California, USA., ISBN:978-1-4673-0321-7, pp: 160-164.

Guo, R. and L.S. DeBrunner, 2011. Two high-performance adaptive filter implementation schemes using distributed arithmetic. IEEE. Trans. Circuits Syst. II. Express Briefs, 58: 600-604.
CrossRef  |  Direct Link  |  

Haykin, S. and B. Widrow, 2003. Least-Mean-Square Adaptive Filters. Vol. 31, Wiley, Hoboken, New Jersey, USA., ISBN:9780471215707,.

Joanna, S.R. and A.V. Anathalakshmi, 2015. Design and implementation of efficient adaptive FIR filter based on distributed arithmetic. Proceedings of the 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), March 19-20, 2015, IEEE, Coimbatore, India, ISBN:978-1-4799-6817-6, pp: 1-4.

Mohanty, B.K., P.K. Meher and S.K. Patel, 2015. LUT optimization for distributed arithmetic-based block least mean square adaptive filter. IEEE. Trans. Large Scale Integr. Syst., 24: 1926-1935.
CrossRef  |  Direct Link  |  

Park, S.Y. and P.K. Meher, 2013. Low-power, high-throughput and low-area adaptive FIR filter based on distributed arithmetic. IEEE. Trans. Circuits Syst. II. Express Briefs, 60: 346-350.
CrossRef  |  Direct Link  |  

Park, S.Y. and P.K. Meher, 2014. Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter. IEEE. Trans. Circuits Syst. II. Express Briefs, 61: 511-515.
CrossRef  |  Direct Link  |  

Prakash, M.S. and R.A. Shaik, 2013. Low-area and high-throughput architecture for an adaptive filter using distributed arithmetic. IEEE. Trans. Circuits Syst. II. Express Briefs, 60: 781-785.
CrossRef  |  Direct Link  |  

White, S.A., 1989. Applications of distributed arithmetic to digital signal processing: A tutorial review. IEEE ASSP Magazine, 6: 4-19.
CrossRef  |  Direct Link  |