Journal of Engineering and Applied Sciences

Year: 2018
Volume: 13
Issue: 13
Page No. 5027 - 5036

Hardware Implementation and Testing of PAPR Reduction Using Order Bit Selector and Trellis Structure

Authors : K.M. Gayathri, S. Bhargavi and N. Thangadurai

Abstract: Orthogonal Frequency Division Multiplexing (OFDM) is one of the well known and widely using multicarrier modulation method in digital communication system. In OFDM, the important parameter to be considered before transmission is to minimize the Peak Average Power Ratio (PAPR). In this study, the design and implementation of OFDM system along with Fragmentary Control Transmit (FCT), order bit selector and trellis structure is used to reduce the PAPR. The modified OFDM system is implemented on an FPGA board. The implementation results show the study of RTL schematic and test bench of the design. The results obtained from the proposed system have been compared with the existing system. It has been observed that the proposed system considerably better than the existing system.

How to cite this article:

K.M. Gayathri, S. Bhargavi and N. Thangadurai, 2018. Hardware Implementation and Testing of PAPR Reduction Using Order Bit Selector and Trellis Structure. Journal of Engineering and Applied Sciences, 13: 5027-5036.

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