Abstract: Accurate extraction of the small-signal equivalent circuit of GaAs microwave Field Effect Transistors (GaAs FET) is crucial for efficient design of microwave analog circuits such as Low Noise Amplifiers (LNAs). This study proposed an improved direct analytical extraction procedure. Its efficiency was demonstrated through the characterisation of two 1 μm gate-length pseudomorphic heterojonction transistors.

INTRODUCTION

Microwave amplifiers constitute an area of prime interest for the high-frequency industry. Most of them use III-V semiconductors such as Gallium Arsenide (GaAs) and Indium Phosphide (InP) because of their higher performance in terms of gain and noise. At the component level, pseudomorphic Heterojonction Transistors (pHEMTs) are widely used in Monolithic Microwave Integrated Circuits (MMICs). The aim of this study is the modeling of such transistors subsequently used to design a low-noise amplifier.

MATERIALS AND METHODS

Small signal equivalent circuit: One of the most widely used small-signal HEMT equivalent circuit is shown in Fig. 1 (Dambrine and Cappy, 1988; Berroth and Bosh, 1990; Anholt and Swirhun, 1991a). According to its structure and operation mode, this circuit can be divided into two parts namely the intrinsic and the extrinsic parts. The intrinsic part corresponds to the active part of the transistor i.e., the channel. The extrinsic part corresponds to the connecting zone (access lines and electrode components).

Extraction of small signal parameters: Determination of the elements of a linear model is based on an experimental characterization of the transistor. The small-signal extraction method proposed in this study is based on S-parameters measurements. It involves the use of 2 sets of measurements at different bias conditions; pinched or cold and hot device measurements.

Fig. 1:	Small signal equivalent circuit of a HEMT

The measured S matri is converted to a impedance matrix (Z) whose elements Z_ij have real and imaginary part: real (Z_ij) and imag (Z_ij) (Freckey, 1994).

The extrinsic elements can be obtained from S-parameters measurements under cold and pinched off biasing conditions: a zero drain source voltage V_ds and a gate source voltage much lower than the pinch-off voltage V_p (i.e., V_ds = 0 V and V_gs << V_p). In fact, cold pinched off bias conditions can simplify the topology of the small signal equivalent circuit as shown in Fig. 2. For more efficiency, the π circuit model in Fig. 2 can be transformed to a T circuit (Caddemi et al., 2006; Anholt and Swirhun, 1991b). Thus, the Z-parameters Z_pij can be expressed as:

(1)

Fig. 2:	Small signal equivalent circuit of HEMT at zero drain bias and gate voltage pinch-off

(2)

(3)

Where, subscript p is pinched off condition. In order to simplify the circuit analysis, the capacitive π network is transformed into a T network consisting of 3 capacitances C_g, C_s and C_d (Caddemi et al., 2006; Anholt and Swirhun, 1991b; Khalaf, 2000):

(4)

(5)

(6)

The parasitic resistances R_g, R_s and R_d can be deduced from the real part of 1, 2 and 3 (Khalaf, 2000). The parasitic inductances L_g, L_s and L_d can be extracted from the slope of the curve of ω* imag (Z_pij) vs. ω² (Caddemi et al., 2006; Khalaf, 2000; Chen et al., 2006; White and Healty, 1993). When the conduction in the channel is removed (i.e., deeply in pinch off V_ds = 0, V_gs << V_p), it is possible to extract the parasitic (extrinsic) capacitances C_pg and C_pd.

Frequencies of some GHz, the effects due to parasitic inductances and resistances can be neglected and thus have little influence on the imaginary parts of the admittance matrix, assuming C_gso = C_gdo and neglecting C_ds (Dambrine and Cappy, 1988; Freckey, 1994; Anholt and Swirhun, 1991b; White and Healty, 1993; Chigaeva et al., 2000). We can write these equations:

(7)

(8)

Once all the extrinsic elements are determined, we can directly extract the intrinsic elements (R_i, C_gs, C_gd, R_ds, C_ds, G_m and τ) from the intrinsic Y-parameters according to the expressions proposed by Dambrine and Cappy (1988), Berroth and Bosh (1990), Khalaf (2000), Chigaeva et al. (2000), Shirakawa et al. (1995) and Wurtz (1994):

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

Where:

Description of device technology: The fabricated high breakdown InGaAs-InAlAs-InP pHEMT (sample-1841) and InGaAs-AlGaAs-GaAs pHEMT (sample-1891) were chosen for this research.

These devices with 1 μm gate length and 200 μm (2x100 μm) gate width are used. The epitaxial layer structure of the used device is shown in Fig. 3. Looking at the structure from bottom to top, a lattice-matched undoped InAlAs buffer layer of thickness 4500 Å is grown on top of an InP semi insulating substrate. A highly strained, undoped InGaAs, channel is grown well below the critical thickness of this composition (140 Å). The spacer is a lattice matched, undoped InAlAs layer of thickness 100 Å used to spatially separate the heavily doped delta-region from the active channel. A supply layer is formed with thickness 150 Å to supply electrons into the 2DEG with Delta-doping sheet density of 3.6x10¹² cm^-2.

Noise figure characterization: The main target of the fabricated devices (GaAs and InP HEMTs and pHEMTs) is the design and implementation of broadband low noise amplifiers for SKA applications. Thus, it is important to get an accurate analytic expression for calculating the minimum noise figure of these devices. Since, the noise figure of a FET is affected by both bias point and generator impedance, the minimum noise figure, NF_min defined here is an absolute minimum noise figure obtained by adjusting both bias and generator impedance.

Using the four equivalent element values Gm, Cgs/Fc Rs and Rg, determined by S-parameter measurement and small-signal parameter extraction Fukui empirically derived a simple expression for NF_min:

(17)

K_f is a fitting factor which depends on the material system used. Applying this empirical form to the fabricated devices used in this study and comparing with experimentally measured NF_min for the same devices, the best extracted fit values for the fitting factor k is 2.8 for the GaAs based samples and 3.4-3.6 for the InP based samples, f is the frequency.

Fig. 3:	Epitaxial layer structure of used transistor (Inp device)

RESULTS AND DISCUSSION

The direct method presented in this research was demonstrated through the extraction of the small-signal equivalent circuit of two pHEMTs. Practically, the values of the extrinsic components were optimized to best fit with measurements (Fig. 4). Table 1 shows the extrinsic and intrinsic element values of the small-signal equivalent circuit of the 2 following pHEMTs: the VMBE- 1841-A132-InP (biased at V_ds = 1.5V and V_gs = -0.2V) and the VMBE-1891-A322-GAs (biased at V_ds = 0.5V and V_gs = - 0.4V). The curves displayed in Fig. 4 showed a good agreement between obtained and measured S-parameters (Table 2). It should be noted that the stability factor k as well as the maximum available gain G _max (with k≥1) or the most stable gain MSG (if k<1) are critical parameters for microwave circuits designers. By comparing the GaAs-pHEMT and the InP-pHEMT it is noted that the InP-pHEMT exhibits a lower minimum noise factor (NF _min) (Fig. 5 and 6), a higher gain G _max and a higher cut-off frequency F_c (Table 3):

Table 1:	Extracted parameter values for the two transistors

Table 2:	Errors between measured and modelled values of S-parameters

Table 3:	Transistor performance parameters

Fig. 4:	Comparison between measured (circles) and calculated (lines) S parameters of pHEMT devices (a, b) VMBE-1841-A132-InP under the bias conditions: Vds = 1.5V, Vgs = -0.2V (c, d) VMBE-1891-A322-GaAs under the bias conditions: Vds = 0.5V, Vgs = -0.4V

Fig. 5:	Comparison of the measured minimum noise figure (room-temperature minimum noise figure of a 1x200 μm device from each sample up to 2 GHz) (circles) with minimum noise figure calculations based on Fukui’s analysis (lines)

Fig. 6:	Maximum Gain Gmax, stability factor K for the: (a) VMBE-1841-A132-InP under the bias conditions: Vds = 1.5V, Vgs = -0.2V (b) VMBE-1891-A322-GaAs under the bias conditions: Vds = 0.5V, Vgs = -0.4V

CONCLUSION

This research presents a direct extraction method of the elements of small signal equivalent circuit of 2 transistors PHEMT one on the GaAs substrate and the other on the InP substrate of which the length and the width of the gate, respectively 1 and 200 μm. This modelling is essential for any active or passive component and which precedes any design of a radio frequency circuit.

The technique suggested is of experimental type, rests to measures of the parameters of dispersion S, followed by a method of optimization with an aim of studying the linear behavior and the performances ultra high frequencies of the transistor. The results obtained show a good agreement between simulated and measured S parameters. The analysis of the performances ultra high frequencies such as the gain, the factor of noise NFmin and the frequency band justifies the choice of transistor pHEMT on the InP substrate for the application low noise.