References

Abella, J., R. Canal and A. Gonzalez, 2003. Power-and complexity-aware issue queue designs. IEEE. Micro, 23: 50-58.
Direct Link  |  

Aggarwal, A., M. Franklin and O. Ergin, 2004. Defining wakeup width for efficient dynamic scheduling. Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors ICCD, October 11-13, 2004, IEEE, New York, USA., ISBN: 0-7695-2231-9, pp: 36-41.

Brekelbaum, E., J. Rupley, C. Wilkerson and B. Black, 2002. Hierarchical scheduling windows. Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, November 18-22, 2002, IEEE Computer Society Press, Istanbul, Turkey, ISBN: 0-7695-1859-1, pp: 27-36.

Brown, M.D., J. Stark and Y.N. Patt, 2001. Select-free instruction scheduling logic. Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture MICRO-34, December 1-5, 2001, IEEE, Austin, Texas, USA., ISBN: 0-7965-1369-7, pp: 204-213.

Buyuktosunoglu, A., D.H. Albonesi, P. Bose, P.W. Cook and S.E. Schuster, 2002. Tradeoffs in power-efficient issue queue design. Proceedings of the 2002 International Symposium on Low Power Electronics and Design, August 12-14, 2002, ACM, Monterey, California, ISBN: 1-58113-475-4, pp: 184-189.

Canal, R. and A. Gonzalez, 2001. Reducing the complexity of the issue logic. Proceedings of the 15th international conference on Supercomputing, June 18-23, 2001, Sorrento, Italy, ISBN: 1-58113-410-X, pp: 312-320.

Do, A.T., S. Chen, Z.H. Kong and K.S. Yeo, 2013. A high speed low power CAM with a parity bit and power-gated ML sensing. IEEE. Trans. Very Large Scale Integr. VLSI. Syst., 21: 151-156.
CrossRef  |  Direct Link  |  

Ernst, D., A. Hamel and T. Austin, 2003. Cyclone: A broadcast-free dynamic instruction scheduler with selective replay. Proceedings of the 30th Annual International Symposium on Computer Architecture, June 9-11, 2003, IEEE, Ann Arbor, Michigan, ISBN: 0-7695-1945-8, pp: 253-262.

Ernst, D., A. Hamel and T. Austin, 2003. Cyclone: A broadcast-free dynamic instruction scheduler with selective replay. Proceedings of the 30th Annual International Symposium on Computer Architecture, June 9-11, 2003, IEEE, Ann Arbor, Michigan, ISBN: 0-7695-1945-8, pp: 253-262.

Folegnani, D. and A. Gonzalez, 2001. Energy-effective issue logic. Proceedings of the 28th Annual International Symposium Computer Architecture, June 30-July 4, 2001, ACM, Gothenburg, Sweden, ISBN: 0-7695-1162-7, pp: 230-239.

Homayoun, H. and A. Baniasadi, 2005. Using lazy instruction prediction to reduce processor wakeup power dissipation. Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 20-22, 2005, IEEE, Austin, Texas, ISBN: 0-7803-8965-4, pp: 0-1.

Hu, J.S., N. Vijaykrishnan and M.J. Irwin, 2004. Exploring wakeup-free instruction scheduling. Proceedings of the International Symposium on High Performance Computer Architectur (HPCA-10), February 14-18, 2004, IEEE, Madrid, Spain, ISBN: 0-7695-2053-7, pp: 232-232.

Hu, Z., A. Buyuktosunoglu, V. Srinivasan, V. Zyuban and H. Jacobson et al., 2004. Microarchitectural techniques for power gating of execution units. Proceedings of the 2004 International Symposium on Low Power Electronics and Design, August 9-11, 2004, ACM, Newport Beach, California, USA., ISBN: 1-58113-929-2, pp: 32-37.

Iwasaki, I., 2008. The determinants of board composition in a transforming economy: Evidence from Russia. J. Corporate Finance, 14: 532-549.
CrossRef  |  Direct Link  |  

Kucuk, G., D. Ponomarev and K. Ghose, 2002. Low-complexity reorder buffer architecture. Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, ACM, New York, USA., ISBN: 1-58113-483-5, pp: 57-66.

Palacharla, S., N.P. Jouppi and J.E. Smith, 1997. Complexity-effective superscalar processors. Proceedings of the 24th annual international symposium on Computer Architecture, June 1-4, 1997, ACM, Denver, Colorado, USA, ISBN: 0-89791-901-7, pp: 206-218.

Raasch, S.E., N.L. Binkert and S.K. Reinhardt, 2002. A scalable instruction queue design using dependence chains. Proceedings of the 29th Annual International Symposium on Computer Architecture, May 25-29, 2002, IEEE Computer Society, New York, USA., ISBN: 0-7695-1605-X, pp: 318-329.

Stark, J., M.D. Brown and Y.N. Patt, 2000. On pipelining dynamic instruction scheduling logic. Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, December 10-13, 2000, ACM, Monterey, California, USA., ISBN: 1-58113-196-8, pp: 57-66.