International Journal of Soft Computing

Year: 2020
Volume: 15
Issue: 5
Page No. 119 - 127

Performance Analysis of EMTCMOS Technique Based D Flip Flop Design at Varied Supply Voltages and Distinct Submicron Technology

Authors : P. Sreenivasulu, K. Srinivasa Rao and A. Vinaya Babu

References

Anis, M., S. Areibi, M. Mahmoud and M. Elmasry, 2002. Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. Proceedings of the 39th Conference on Design Automation, New Orleans, Louisiana, USA., June 10-14, 2002, ACM, New York, USA., pp: 480-485.

De, V. and S. Borkar, 1999. Technology and design challenges for low power and high performance. Proceedings of the 1999 International Symposium on Low Power Electronics and Design, August 17, 1999, ACM, San Diego, California, pp: 163-168.

Kuroda, T., T. Fujita, S. Mita, T. Nagamatu and S. Yoshioka et al., 1996. A 0.9 V, 150 MHZ, 10 mW, 4 mm 2,2-D Discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE J. Solid-State Circuits, 31: 166-167.
Direct Link  |  

MP, P.K. and A.A. Fletcher, 2014. A survey on leakage power reduction techniques by using power gating methodology. Int. J. Eng. Trends Technol. (IJETT.)., 9: 566-571.

Mutoh, S.I., T. Douseki, Y. Matsuya, T. Aoki and S. Shigematsu et al., 1995. 1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS. IEEE. J. Solid State Circuits, 30: 847-854.
CrossRef  |  Direct Link  |  

Naidu, U.S. and K. Venkateswarlu, 2013. A novel approach power optimized multi-bit flip-flops using gated driver tree. Int. J. Adv. Res. Electr. Electron. Instrum. Eng., 2: 2721-2725.
Direct Link  |  

Nedovic, N., M. Aleksic and V.G. Oklobdzija, 2001. Conditional techniques for low power consumption flip-flops. Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems ICECS (Cat. No. 01EX483), September 2-5, 2001, IEEE, Malta, pp: 803-806.

Nehra, S. and P.K. Ghosh, 2013. Design of a low power XNOR gate using MTCMOS technique. Adv. Electron. Eng., 3: 701-710.
Direct Link  |  

Nirmal, U., G. Sharma and Y. Misra, 2011. A low power high speed adders using MTCMOS technique. IJCEM. Int. J. Comput. Eng. Manage., 13: 65-69.
Direct Link  |  

Oskuii, S.T., 2003. Comparative study on low-power high-performance flip-flops. Master Thesis, Linkoping University, Linkoping Sweden.

Ramanarayanan, R., N. Vijaykrishnan and M.J. Irwin, 2002. Characterizing dynamic and leakage power behavior in flip-flops. Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, September 25-28, 2002, IEEE, Rochester, New York, pp: 433-437.

Rani, M.J. and S. Malarkann, 2012. Leakage power reduction and analysis of CMOS sequential circuits. Int. J. VLSI Des. Commun. Syst., 3: 13-23.

Roy, K. and S.C. Prasad, 2000. Low Power CMOS VLSI Circuit Design. 1st Edn., Wiley, New York, ISBN-10: 047111488X, pp: 376.

Shigematsu, S., 1995. A I-V high-speed MTCMOS circuit scheme for power-down applications. VLSI Symp. Digest Tech. Pap., 1: 125-126.

Singh, G. and V. Sulochana, 2013. Low power dual edge-triggered static D flip-flop. Int. J. VLSI Des. Commun. Syst. (VLSICS.), Vol. 4, No. 3.

Sultana, T., S. Jagadeesh and M.N. Kumar, 2013. A novel dual stack sleep technique for reactivation noise suppression in MTCMOS circuits. IOSR. J. VLSI Signal Process. (IOSR-JVSP.), 3: 32-37.
Direct Link  |  

Design and power by Medwell Web Development Team. © Medwell Publishing 2024 All Rights Reserved