References

Agrawal, G.R., L.W. Massengill and K. Gulati, 1994. A proposed SEU tolerant dynamic random access memory (DRAM) cell. IEEE Trans. Nucl. Sci., 41: 2035-2042.
CrossRef  |  Direct Link  |  

Akter, M., M.B.I. Reaz, F. Mohd-Yasin and F. Choong, 2008. A modified-set partitioning in hierarchical trees algorithm for real-time image compression. J. Commun. Technol. Electr., 53: 642-650.
CrossRef  |  Direct Link  |  

Akter, M., M.B.I. Reaz, F. Mohd-Yasin and F. Choong, 2008. Hardware implementations of an image compressor for mobile communications. J. Commun. Technol. Electr., 53: 899-910.
CrossRef  |  Direct Link  |  

Cao, C.W., S.G. Zang, X. Lin, Q.Q. Sun, C. Xing, P.F. Wang and D.W. Zhang, 2012. A novel 1T-1D DRAM cell for embedded application. IEEE Trans. Electron Devices, 59: 1304-1310.
CrossRef  |  Direct Link  |  

Chang, I.J., J.J. Kim, S.P. Park and K. Roy, 2009. A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. IEEE J. Solid-State Circuits, 44: 650-658.
CrossRef  |  Direct Link  |  

Chun, K.C., P. Jain, T.H. Kim and C.H. Kim, 2012. A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches. IEEE J. Solid-State Circuits, 99: 1-13.

Diodato, P.W., J.T. Clemens, W.W. Troutman and W.S. Lindenberger, 1997. A reusable embedded DRAM macrocell. Proceedings of the IEEE Custom Integrated Circuits Conference, May 5-8, 1997, Murray Hill, New Jersey, pp: 337-340.

Leiss, J.E., P.K. Chatterjee and T.C. Holloway, 1982. dRAM design using the taper-isolated dynamic RAM cell. IEEE Trans. Electron Devices, 29: 707-714.

Luk, W.K., J. Cai, R.H. Dennard, M.J. Immediato and S.V. Kosonocky, 2006. A 3-transistor DRAM cell with gated diode for enhanced speed and retention time. Proceedings of the Symposium on VLSI Circuits, June 15-17, 2006, New York, USA., pp: 184-185.

Marufuzzaman, M., M.B.I. Reaz, M.S. Rahman and M.A.M. Ali, 2010. Hardware prototyping of an intelligent current dq PI controller for FOC PMSM drive. Proceedings of 6th International Conference on Electrical and Computer Engineering, December 18-20, 2010, Dhaka, Bangladesh, pp: 86-88.

Mogaki, S., M. Kamada, T. Yonekura, S. Okamoto, Y. Ohtaki and M.B.I. Reaz, 2007. Time-stamp service makes real-time gaming cheat-free. Proceedings of the 6th Annual Workshop on Network and Systems Support for Games: Netgames 2007, September 19-20, Melbourne, Australia, pp: 135-138.

Mohd-Yasin, F., A.L. Tan and M.I. Reaz, 2004. The FPGA prototyping of iris recognition for biometric identification employing neural network. Proceedings of the 16th International Conference on Microelectronics, December 6-8, 2004, Tunis, Tunesia, pp: 458-461.

Reaz, M.B.I. and L.S. Wei, 2004. Adaptive linear neural network filter for fetal ECG extraction. Proceedings of the International Conference on Intelligent Sensing and Information Processing, January 4-7, 2004, Chennai, India, pp: 321-324.

Reaz, M.B.I., F. Choong and F. Mohd-Yasin, 2006. VHDL modeling for classification of power quality disturbance employing wavelet transform, artificial neural network and fuzzy logic. Simulation, 82: 867-888.
CrossRef  |  

Reaz, M.B.I., F. Choong, M.S. Sulaiman and F. Mohd-Yasin, 2007. Prototyping of wavelet transform, artificial neural network and fuzzy logic for power quality disturbance classifier. Electr. Power Components Syst., 35: 1-17.
CrossRef  |  Direct Link  |  

Reaz, M.B.I., F. Mohd-Yasin, S.L. Tan, H.Y. Tan and M.I. Ibrahimy, 2005. Partial encryption of compressed images employing FPGA. Proceedings of the IEEE International Symposium on Circuits and Systems, May 23-26, 2005, Kobe, Japan, pp: 2385-2388.

Reaz, M.B.I., M.I. Ibrahimy, F. Mohd-Yasin, C.S. Wei and M. Kamada, 2007. Single core hardware module to implement encryption in TECB mode. Informacije MIDEM J. Microelect. Electron Compon. Mater., 37: 165-171.

Reaz, M.B.I., M.T. Islam, M.S. Sulaiman, M.A.M. Ali, H. Sarwar and S. Rafique, 2003. FPGA realization of multipurpose FIR filter. Proceedings of the Parallel and Distributed Computing, Applications and Technologies, August 27-29, 2003, Chengdu, pp: 912-915.

Tsuchiya, T. and M. Itsumi, 1982. New dynamic RAM Cell for VLSI memories. IEEE Electron Device Lett., 3: 7-10.
CrossRef  |  

Verma, N. and A.P. Chandrakasan, 2008. A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy. IEEE J. Solid-State Circuits, 43: 141-149.
Direct Link  |  

Xie, Y., 2011. Modeling, architecture and applications for emerging memory technologies. IEEE Design Test Comput., 28: 44-51.
Direct Link  |