References

Anonymous, 2014. 9 Reasons why the Vivado design suite accelerates design productivity. Xilinx, San Jose, California, USA. https://www.xilinx.com/publications/prod_mktg/vivado/Vivado_9_Reasons_Backgrounder.pdf

Ha, S., C. Lee, Y. Yi, S. Kwon and Y.P. Joo, 2006. Hardware-software co-design of multimedia embedded systems: The peaCE. Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, August 16-18, 2006, IEEE, Sydney, Australia, ISBN:0-7695-2676-4, pp: 207-214.

Karthik, S., S. Saravanakumar, G Murali and Gokulnath, 2015. Parallel HDL simulation using heterogeneous FPGA architectures. Intl. J. Appl. Eng. Res., 10: 18219-18222.

Karthik, S., S.S. Kumar and K. Priyadarsini, 2015. Comparative study of homogeneous and heterogeneous processor in FPGA for functional verification. Intl. J. Appl. Eng. Res., 10: 38358-38361.

Kim, D., M. Ciesielski and S. Yang, 2013. MULTES: Multilevel temporal-parallel event-driven simulation. IEEE. Trans. Comput. Aided Des. Integr. Circuits Syst., 32: 845-857.
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Lam, W.K.C., 2005. Hardware Design Verification: Simulation and Formal Method-based Approaches. Prentice Hall, Upper Saddle River, New Jersey, USA., ISBN:9780131433472, Pages: 585.

Li, T., S. Li, F. Ao and G. Li, 2004. Parallel verilog simulation: Architecture and circuit partition. Proceedings of the 2004 International Conference on Asia and South Pacific Design Automation, January 27-30, 2004, IEEE, Piscataway, New Jersey, ISBN:0-7803-8175-0, pp: 644-646.

Xilinx, 2008. Embedded System Tools Reference Manual: Embedded Development Kit. Xilinx, San Jose, California, USA, Pages: 294.

Zhu, L., G. Chen, B.K. Szymanski, C. Tropper and T. Zhang, 2005. Parallel logic simulation of million-gate VLSI circuits. Proceedings of the 2005 13th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, September 27-29, 2005, IEEE, Atlanta, Georgia, ISBN:0-7695-2458-3, pp: 521-524.